CAT24C03YI-GT3中文资料

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FEATURES

DEVICE DESCRIPTION

The CAT24C03 is a 2-Kb Serial CMOS EEPROM, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits each.

It features a 16-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol.

Write operations can be inhibited by taking the WP pin High (this protects the upper half of the memory).The CAT24C03 is available in RoHS compliant “Green” and “Gold” 8-lead PDIP, SOIC, TSSOP and TDFN packages.

■ Supports Standard and Fast I2C Protocol ■ 1.8 V to 5.5 V Supply Voltage Range■ 16-Byte Page Write Buffer

■ Hardware Write Protection for upper half of

memory

■ Schmitt Triggers and Noise Suppression Filters

on I2C Bus Inputs (SCL and SDA).

■ Low power CMOS technology■ 1,000,000 program/erase cycles■ 100 year data retention■ RoHS compliant

8-pin PDIP &

■ Industrial temperature range

PIN CONFIGURATION

PDIP (L)SOIC (W)TSSOP (Y)TDFN (VP2)

A0A1A2VSS

1234

8765

VCCWPSCLSDA

FUNCTIONAL SYMBOL

VCC

SCL

A2, A1, A0

WP

SDA

For the location of Pin 1, please consult the corresponding package drawing.

PIN FUNCTIONS

A0, A1, A2SDASCLWPVCCVSS

Device AddressSerial DataSerial ClockWrite ProtectPower SupplyGround

VSS

* Catalyst carries the I2C protocol under a license from the Philips Corporation.

© 2006 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

1

Doc. No. 1113, Rev. A

元器件交易网http://doc.guandang.net

ABSOLUTE MAXIMUM RATINGS* Storage Temperature

Voltage on Any Pin with Respect to Ground(1)

-65°C to +150°C-0.5 V to +6.5 V

* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci cation is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

RELIABILITY CHARACTERISTICS(2)SymbolNEND(*)TDR

ParameterEnduranceData Retention

Min1,000,000100

Units

Program/ Erase Cycles

Years

(*) Page Mode, VCC = 5 V, 25°C

D.C. OPERATING CHARACTERISTICS

VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise speci ed. SymbolICCISBILVILVIHVOL1VOL2

ParameterSupply CurrentStandby CurrentI/O Pin LeakageInput Low VoltageInput High VoltageOutput Low VoltageOutput Low Voltage

VCC > 2.5 V, IOL = 3.0 mAVCC > 1.8 V, IOL = 1.0 mATest ConditionsRead or Write at 400 kHzAll I/O Pins at GND or VCCPin at GND or VCC

-0.5Min

Max122VCC x 0.3

UnitsmAμAμAVVVV

VCC x 0.7VCC + 0.5

0.40.2

PIN IMPEDANCE CHARACTERISTICSTA = 25°C, f = 400 kHz, VCC = 5 VSymbolCIN(2)CIN(2)ZWPLILWPH

Note:

(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may

undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100

and JEDEC test methods.

Parameter

SDA I/O Pin CapacitanceInput Capacitance (other pins)WP Input Low ImpedanceWP Input High Leakage

ConditionsVIN = 0 VVIN = 0 VVIN < 0.5 VVIN > VCC x 0.7

MinMax86

UnitspFpFkΩμA

5702

Doc. No. 1113, Rev. A

2

© 2006 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

元器件交易网http://doc.guandang.net

A.C. CHARACTERISTICS

VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise speci ed.

1.8 V - 5.5 V

SymbolFSCLTI(1)tAA(2)tBUF(1)tHD:STAtLOWtHIGHtSU:STAtHD:DATtSU:DATtR(1)tF(1)tSU:STOtDHtWRtPU(1), (3)

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) For timing measurements the SDA line capacitance is ~ 100 pF; the SCL input is driven with rise and fall times of < 50 ns; the SDA I/O

is pulled-up by a 3 mA current source; input driving signals swing from 20% to 80% of VCC. Output level reference levels are 30% and respectively 70% of VCC.(3) tPU is the delay required from the time VCC is stable until the device is ready to accept commands.

2.5 V - 5.5 VMin

Max4000.10.9

1.30.61.30.60.600.1

UnitskHzμs μs μs μsμsμsμs μsμs

0.30.3

0.60.1

μsμsμsμs

51

msms

ParameterClock Frequency

Noise Suppression Time Constant at SCL, SDA Inputs

SCL Low to SDA Data Out

Time the Bus Must be Free Before a New Transmission Can StartStart Condition Hold TimeClock Low PeriodClock High PeriodStart Condition Setup TimeData In Hold TimeData In Setup TimeSDA and SCL Rise TimeSDA and SCL Fall TimeStop Condition Setup TimeData Out Hold TimeWrite Cycle TimePower-up to Ready Mode

MinMax1000.13.5

4.744.744.700.25

10.3

40.1

51

Power-On Reset (POR)

The CAT24C03 incorporates Power-On Reset (POR)

circuitry which protects the internal logic against

powering up in the wrong state.

The CAT24C03 will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR feature protects the device against ‘brown-out’ failure following a temporary loss of power.

The POR circuitry triggers at the minimum VCC level requir …… 此处隐藏：14381字，全部文档内容请下载后查看。喜欢就下载吧 ……