现代交换技术实验指导书(2)

数字程控交换实验指导书

实验二 程控交换PCM编译码实验

一、实验目的

1．掌握PCM编译码器在程控交换机中的作用；

2．熟悉单片PCM编译码集成电路TP3057的电路组成和使用方法； 3．观测TP3057各测量点的工作波形。

二、电路组成

电话用户电路的模拟信号与数字信号的变换是通过PCM编译码器码器完成的。PCM（脉冲编码调制）就是把一个时间连续、取值连续的模拟信号变换成时间离散、取值离散的数字信号后在信道中传输。脉冲编码调制是对模拟信号进行抽样，量化和编码。本实验中采用TP3057集成电路完成PCM编码和译码功能。关于TP3057更详细的技术资料可到网上查询, 由于详细精确的芯片资料大部分都是英文版本，所以这里要求学生具备一定英文资料查阅能力。

General Description：The TP3057 family consists of A-law monolithic PCM CODEC/filters utilizing the A/D and D/A conversion architecture shown in Figure 1, and a serial PCM interface. The devices are fabricated using National's advanced double-poly CMOS process (microCMOS). The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded m-law or A-law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded m-law or A-law code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads. The devices require two 1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks, which may vary from 64 kHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats。

实验中的TP3057芯片工作时序控制采用短帧非同步法。

SHORT FRAME SYNC OPERATION：The COMBO can utilize either a short frame sync

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数字程控交换实验指导书

pulse or a long frame sync pulse. Upon power initialization, the device assumes a short frame mode. In this mode, both frame sync pulses, FSX and FSR, must be one bit clock period long, with timing relationships specified in Figure 2. With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the remaining seven bits, and the next falling edge disables the DX output. With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following seven falling edges latch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous orasynchronous operating mode。 …… 此处隐藏：682字，全部文档内容请下载后查看。喜欢就下载吧 ……