基于FPGA的红外线型学习遥控器(3)

data:in std_logic_vector(31 downto 0); anjian1:in std_logic; anjian2:in std_logic; anjian3:in std_logic;

od:out std_logic_vector(15 downto 0); ad:out std_logic_vector(4 downto 0)); end entity;

architecture behav of hw_address is type state is(s0,s1,s2,s3); signal sta:state;

signal addr:std_logic_vector(4 downto 0); begin ad<=addr;

process(anjian1,anjian2,anjian3,clk) begin

if(anjian1='1'and anjian2='1'and anjian3='1')then sta<=s0; od<=x\addr<=\

elsif(clk'event and clk ='1')then case sta is

when s0=>if(anjian1='0')then od<=x\ addr<=\ sta<=s1;

elsif(anjian2='0')then od<=x\ addr<=\ sta<=s1;

elsif(anjian3='0')then od<=x\ addr<=\ sta<=s1; end if; when s1=>addr<=addr;

od<=data(15 downto 0); sta<=s2; when s2=>addr<=addr+'1';

od<=data(31 downto 16); sta<=s3; when s3=>sta<=s3; end case;

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end if; end process; 存储读出程序

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hw_adout is port(clk:in std_logic;

inin:in std_logic_vector(15 downto 0); anjian1:in std_logic; anjian2:in std_logic; anjian3:in std_logic;

output:out std_logic_vector(31 downto 0)); end entity;