7023 Programming Guide_RegTab1.5

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Chrontel

Rev 1.5 07/19/2006

1

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Table of Contents

Chip Identification.….…………………………………………………………………………3

System Configuration…………………………………………………………………………3

Sync Control……………………………..………………………………………………3

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CHIP IDENTIFICATION

The CH7023/4 is a device targeting handheld and similar systems which accepts a digital input

signal, and encodes and transmits data through 10-bit DACs. The device is able to encode the

video signals and generate synchronization signals for NTSC and PAL standards. The device

accepts different data formats including RGB and YCrCb (e.g. RGB565, RGB666, RGB888,

ITU656 like YCrCb, etc.).

HPO, VPO

HPO(0x0E[3] ) defines the polarity of horizontal sync. When HPO is ‘1’, the polarity is

positive; otherwise is negative.

VPO(0x0E[2] ) defines the polarity of vertical sync. When VPO is ‘1’, the polarity is positive;

otherwise is negative.

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SYO

SYO (0x0E[1]) defines the direction of sync. When SYO is ‘0’, input sync; otherwise output

sync.

CLOCK SETTING

frequency is predefined, some registers, such as SCFREQ, will be calculated inside the chip

to save programming effort.

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0: Using predefined value.

1: Using other value.

When XTALSEL set to predefined value, XTAL[3:0] ( bits 3-0 ) have to program follow by

the table below:

0: Outputs are not dual CVBS.

1: outputs are dual CVBS, and meanwhile, the SVD/DDAC (bit 6 of 0Ah) should be set

to ‘1’, and DACSW[1:0] (0Ah[5:4]) should be set to ‘10’.

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SEL_R

Address:

63h

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USING UTILITY

The Register Table utility is created to help software engineer program PLL1N1, PLL2N2,

PLL3N3, PLL3N4, PLL3N5, A, P, T, N, SCFREQ, HTI and VTI registers of

CH7023/CH7024. The following section explains how to use Register Table utility step by step.

Run the utility Setting Wizard and the popup dialog box is as figure A.

Figure B

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How to calculate

There are six steps to complete the calculation as reference page number indicated below:

Step 1 Program System configuration registers: Page 7

Step 2 Program PLL1N1, PLL2N2, PLL3N3 ,PLL3N4 ,PLL3N5 and A registers: Page 8.

Step 3 Decide H-Total and V-Total: Page 10

Step 4 Program P, N and T piders registers: Page 11

o TV_Format: Choose Video Output Format.

o : Defines the allowable deviation of real UCLK from the

standard UCLK (27MHz); default tolerance is 0.01%.

o XCLK : Equals pixel clock or twice pixel clock. See “XCH”.

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o Pout CLK: When work on master mode CH7023/CH7024 output as reference

clock.

o HAI,VAI: Define input horizontal active pixel and vertical active pixel.

Step 2: After filled up the required information on step1. Click on “Input” button, all

supported modes should be listed out on list box as well as PLL1N1, PLL2N2,

PLL3N3, PLL3N4, PLL3N5 and A settings. PLL1N1, PLL2N2, PLL3N3, PLL3N4,

PLL3N5 decide the values of r1, r2, r3, r4 and r5 separately. Write the calculated

settings into following registers.

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PLL1N1, PLL2N2, PLL3N3, PLL3N4 and PLL3N5

7 6 5 4 3 2 1 0

A[15] A[8]

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Address: 27h

7 6 5 4 3 2 1 0

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Chrontel

CH7023/CH7024 Programming Guide

Figure D Step 3: Double click the mode selected then the new dialog (Figure D) will pop up to confirm the selection. Click OK button on the new dialog and P, N and T clock piders setting will be generated (Figure E).

Rev 1.5

07/19/2006

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The values of M and N are the coefficient to generate UCLK from XCLK. Address: 28h

7 6 5 4 3 2 1 0

P[22] P[21]

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Address: 29h

7 6 5 4 3 2 1 0

P[8] P[14] P[13] P[10] P[9]

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Chrontel

CH7023/CH7024 Programming Guide

Figure F

Step 5: Write SCFREQ from registers 0x34 to 0x37 when ACIV bit (0x1C[4]) is set to“1”. Please refer to section of Sub-carrier generation for more detail.

Rev 1.5

07/19/2006

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Chrontel

CH7023/CH7024 Programming Guide

Address: 34h BIT: 7 6 5 4 3 2 1 0 SYMBOL Reserved Reserved Reserved Reserved Reserved SCFREQ[ SCFREQ[ SCFREQ[: 26] 25] 24] TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAUL 0 0 0 0 0 0 0 1 Address: 35h 7 6 5 4 3 2 1 0 BIT: SYMBOL SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[: 23] 22] 21] 20] 19] 18] 17] 16] TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAUL 0 0 0 1 1 0 0 1 Address: 36h 7 6 5 4 3 2 1 0 BIT: SYMBOL SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[: 15] 12] 11] 10] 9] 14] 13] 8] TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAUL 1 1 1 1 0 1 0 1 Address: 37h

BIT: 7 6 5 4 3 2 1 0 SYMBOL SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAUL 0 0 1 1 1 1 1 1 SCFREQ[26:0], the Sub-carrier Frequency Value.

Rev 1.5

07/19/2006