STM32 PMSM FOC SDK_Part7(共11份)

STM32 PMSM FOC 库的讲解,视频讲义

Agenda 1st day– Afternoon MC Application Interface Tuning Tasks Classes interaction Current regulation Ramp-up Encoder alignment

1

Speed sensors updates: Sensorless algorithm improvement

How to create User Project Interacting with MC Application Dual motor control Resources sharing Supported configurations Code size efficiency

Current reading sensor update

STM32 PMSM FOC SDK v3.2

29/03/2013

STM32 PMSM FOC 库的讲解,视频讲义

Dual motor control requirements In present implementation of dual FOC, two advanced timers are required (this limit the feasibility to big piranha) Consider that CPU is shared between the two controls FOC execution (i.e. CPU utilization) related to each of the drives must be synchronous with the related PWM signal Depending on current sensing HW topology, ADC peripherals could also require to be shared (e.g. 2x three shunts)

2

This limit the possible configurations and force to take some design decisions: The two drive must have PWM frequencies multiple one of the other The two drive may have different repetition counters The two timers must be synchronized so that the update events of the timers do not overlap (related to present implementation)STM32 PMSM FOC SDK v3.2 29/03/2013

STM32 PMSM FOC 库的讲解,视频讲义

ADC peripherals usage When possible ADCs peripherals have been dedicated to a given drive so that - in its turn - a drive can have dedicated ADC(s) When not possible a mechanism for sharing ADCs between the drive must be put in place

3

Three shunts and ICS current reading HW topology requires two ADCs (so as to perform simultaneous sampling of two currents) Single shunt drive requires only one ADC Motor 1 Motor 2 Three shunts ICS Three shunts ICS ADC1: Three shunt/ICS* ADC2: Three shunt/ICS* ADC3: Single shunt

ADC1: Three shunt/ICS ADC2: Three shunt/ICS ADC3: Single shunt ADC1: Single shunt ADC2: ADC3: Single shuntSTM32 PMSM FOC SDK v3.2 29/03/2013

Single shunt

ADC1: Three shunt/ICS ADC2: Three shunt/ICS ADC3: Single shunt

* Shared resources

STM32 PMSM FOC 库的讲解,视频讲义

ADC peripherals sharing: basics If at least one drive is in single shunt topology no resources sharing is required No limitations occur in this case

4

In case of dual three-shunts, ICS or any combination of them Drives must not require ADCs usage at the same time PWM patterns should be properly shifted each other

There must be a moment where ADCs are re-configured so as to serve a given drive For instance the set of channels to be converted and the triggering event must be re-configured

This moment will be referred as‘context switching’

STM32 PMSM FOC SDK v3.2

29/03/2013

STM32 PMSM FOC 库的讲解,视频讲义

ADC peripheral sharing When context switching should be performed? 3 shunts and ICS configurations require ADC conversions to be executed synchronously with PWM

5

More precisely conversions must be performed: With the same occurrence rate of the Update events (i.e. once each 1

, 2, 3,… PWM periods) In case of 3 shunts, conversions must be performed in proximity of the counter crest (where the three low side switches are closed and the related currents accessible) For simplicity, in case of ICS as well current conversions are executed on counter crest

In present implementation it has been decided to perform context switching in the TIMx Update ISR leading by half PWM period the ADC usageTIM1

U

U

ADC1 and ADC2 in use

STM32 PMSM FOC SDK v3.2

29/03/2013

STM32 PMSM FOC 库的讲解,视频讲义

TIMx Update ISR: switch context algorithmDrive1 TIM1

6

U

U

U

U

Drive2 TIM8

UDriver1 Trigger range TW2 Driver2 Trigger range

UDriver1 Trigger range Driver2 Trigger range

U

UDriver2 Trigger range TW1 Driver1 Trigger range TW2

Driver1 Trigger range

TW1

TW2

TW1

TW2

Twn is the maximum delay between counter crest and latest conversion in drive nSwitch context algorithm Check ADC1 JSTRT and JEOC bits Check ADC1 JSTRT and JEOC bits JSTRT 1 JEOC 1 JSTRT 1 JEOC 0 JSTRT 0 JEOC 0 Change ADC triggers, channels, sampling time

JSTRT 1 JEOC 1

JSTRT 1 JEOC 0

JSTRT 0 JEOC 0

NIs JEOC set?

Wait maximum delay Twn

N

Is JEOC set?

Y

YSTM32 PMSM FOC SDK v3.2 29/03/2013

STM32 PMSM FOC 库的讲解,视频讲义

Example 1, drives have same fPWMDrive1 TIM1

7

U

U

U

U

Drive2 TIM8

UDriver1 Trigger range TW2 Driver2 Trigger range

UDriver1 Trigger range Driver2 Trigger range

U

UDriver2 Trigger range TW1 Driver1 Trigger range TW2

Driver1 Trigger range

TW1

TW2

TW1

TW2

TIM1_CH4

ADC Start

ADC Start

ADC Start

ADC Start

ADC Start TIM8_CH4 Delay ISR TIM8 Up. Delay ISR TIM1 Up. Delay ISR TIM8 Up.

ADC Start

ADC Start

Delay ISR TIM1 Up.

Delay ISR TIM8 Up.

Delay ISR TIM1 Up.

Delay ISR TIM8 Up.

During TIMx Update event ISR, it’s necessary to wait for ADC to finish conversions before switching the contextSTM32 PMSM FOC SDK v3.2 29/03/2013

STM32 PMSM FOC 库的讲解,视频讲义

Example 2 fPWM1= 2*fPWM2 For drive 1 fPWM1/ fFOC1= 2 (FOC executed each 2 PWM cycles) For drive 2 fPWM2/ fFOC2= 1 (FOC executed each PWM cycle)Drive1 TIM1

8

U

U

U

Drive2 TIM8

UDriver1 Trigger range Driver2 Trigger range

UDriver1 Trigger range Driver2 Trigger range

TIM1_CH4

ADC Start

ADC Start

ADC Start TIM8_CH4 Delay ISR TIM8 Up. Delay ISR TIM1 Up. Delay ISR TIM8 Up.

ADC Start

STM32 PMSM FOC SDK v3.2< …… 此处隐藏：6134字，全部文档内容请下载后查看。喜欢就下载吧 ……